1. Field of the Invention
The present invention relates generally to Metal-Oxide-Semiconductor (MOS) field effect transistors and, more particularly, to an improved MOS field effect transistor in which no distortion occurs in a semiconductor substrate, and further to a method of manufacturing such a MOS field effect transistor.
2. Description of the Background Art
MOS field effect transistors (hereinafter referred to as MOSFETs) serve as devices for controlling the flow of a large number of carriers by a voltage to be applied to gates in such a manner as to regulate the amount of water by opening/closing a valve of a water pipe.
FIG. 11 is a cross-sectional view showing a fundamental structure of a conventional MOSFET. Referring to FIG. 11, a gate 2 is provided on a semiconductor substrate 1. A source 3 and a drain 4 are formed on the opposite sides of gate 2, respectively, in a main surface of semiconductor substrate 1. With a voltage to be applied to gate 2, a channel region 5 directly beneath gate 2 is inverted to render source 3 and drain 4 conductive. In the MOSFET having the above-described structure, when a channel length is short, a depletion layer 6 in the vicinity of drain 4 extends over source region 3, so that a current fails to be controlled by the voltage of gate 2. This phenomenon is called a punch-through of MOSFET. In FIG. 11, a portion denoted with a reference number 7 is an end portion of the depletion layer.
In order to prevent this punch-through, such a semiconductor device has been proposed that MOSFETs are formed in wells. FIG. 12A is a cross-sectional view of a conventional semiconductor device in which a buried channel MOSFET is formed in a well formed in a semiconductor substrate. FIG. 13 is a plan view of the semiconductor device shown in FIG. 12A. Referring to these figures, an n type impurity diffusion layer 8 called "a well" is formed in a main surface of a p.sup.- semiconductor substrate 1. The definition of p type and n type will be described later. An impurity layer 9 for controlling a threshold voltage is provided in a surface portion of impurity diffusion layer 8. A gate 2 implanted with n type impurity ions is provided on semiconductor substrate 1. A source 3 and a drain 4 formed with diffused p type impurities are provided on the opposite sides of gate 2 in impurity diffusion layer 8. A field oxide film 10 provided in the main surface of semiconductor substrate 1 serves to isolate an elementary device region 11 from the other elementary device regions. In the conventional MOSFET thus structured, since source 3 and drain 4 are formed in the well having the opposite conductivity type (n type impurity diffusion layer 8), even a shorter channel length does not cause the depletion layer in the vicinity of drain 4 to extend over source region 3, resulting in an effective protection of punch-through.
A brief description will be given of the buried channel MOSFET of FIG. 12A.
FIG. 12B is a graph showing the distribution of the number of ions existing in the main surface of the semiconductor substrate, plotted with respect to a distance in the direction of a channel length. In the graph, a longitudinal axis denotes the number of ions defined in the following, and a lateral axis denotes the distance in the direction of the channel length.
N=n.sub.N -n.sub.p PA1 P=n.sub.p -n.sub.N
In the above expressions, n.sub.N and n.sub.P denote the number of n type atoms and that of p type atoms, respectively. If the relation n.sub.N -n.sub.P &gt;0 is satisfied in a certain region, N&gt;0 is satisfied. This region is an n type impurity region from the viewpoint of metallurgy. If the relation n.sub.p -n.sub.N &gt;0 is satisfied in a region, P&gt;0 is satisfied. This region is a p type impurity region from the viewpoint of metallurgy.
With reference to FIGS. 12A and 12B, a portion directly beneath gate 2, i.e., a channel region is of p.sup.- type metallurgically. Thus, source 3 and drain 4 appear to be conductive already at first sight even if no voltage is applied to gate 2. However, gate 2 is implanted with n type impurities, and hence this electric field causes the potential of the channel region to be of n type, with reference to FIG. 12C. More specifically, source region 3 and drain region 4 are electrically isolated from each other, with n type gate 2 mounted on semiconductor substrate 1. Applying a positive voltage to gate 2 causes the potential of the channel region to be of p type and renders source region 3 and drain region 4 conductive.
A method of manufacturing the conventional MOSFET shown in FIG. 12A will now be described with reference to FIGS. 14A-14E.
Referring to FIG. 14A, n type impurity ions 12 (phosphorus) are implanted into the overall surface of a p type semiconductor substrate 1 (boron, 1.times.10.sup.15 cm.sup.-3). The ion-implanted substrate is then subjected to a thermal diffusion at 1000.degree. C. or more for 10 hours, thereby to form an n type impurity diffusion layer 8 (phosphorus, 1.times. 10.sup.16 cm.sup.-3), which is called a well, in the main surface of semiconductor substrate 1.
Then, p type impurity ions 13 (boron) are implanted into the overall surface of impurity diffusion layer 8, thereby to form an impurity layer 9 for controlling a threshold voltage (boron, 1.times.10.sup.17 cm.sup.-3) in the surface of impurity diffusion layer 8, as shown in FIG. 14B.
Referring to FIG. 14C, semiconductor substrate 1 undergoes a thermal oxidation processing, whereby a gate oxide film 14 is formed on the surface of semiconductor substrate 1. Thereafter, an electrode material containing n type impurity ions (not shown) is deposited on gate oxide film 14 and then patterned in a predetermined form, thereby to form an n type gate 2.
An oxide film (not shown) is then deposited on the overall surface of semiconductor substrate 1 including gate 2, and then subjected to an anisotropical etching, thereby forming sidewall spacers 15 on sidewalls of gate 2, with reference to FIG. 14D.
As shown in FIG. 14E, with gate 2 and sidewall spacers 15 used as mask, p type impurity ions 16 (boron) are implanted into the surface of semiconductor substrate 1, so as to form a source region 3 (boron 1.times.10.sup.20 cm.sup.-3) and a drain region 4 (boron, 1.times.10.sup.20 cm.sup.-3) in the surface of impurity diffusion layer 8.
An interlayer insulation film is then formed (not shown) on the overall surface of semiconductor substrate 1 including gate 2. Thereafter, a contact hole is formed in this interlayer insulation film, and then an aluminum interconnection is formed, thereby forming an MOSFET.
The conventional MOSFET structured in the above-described manner must be subjected to a heat treatment at a high temperature of 1000.degree. C. or more in order to form n type impurity diffusion layer 8 to be the well, with reference to FIGS. 12A and 14A. This high-temperature heat treatment produces stresses in semiconductor substrate 1 due to thermal stresses which remain as residual stresses in the semiconductor substrate even if the temperature returns to a normal temperature. The residual stresses cause a distortion of semiconductor substrate 1. A tendency that the semiconductor substrate is distorted by the residual stresses increases as the semiconductor substrate has a larger diameter. The distortion of the semiconductor substrate results in the occurrence of unevenness and unstableness in process between central portion and peripheral portion of the semiconductor substrate. Consequently, the difference in characteristic of the device occurs between the central portion and the peripheral portion of the semiconductor substrate, leading to a disadvantage of causing a decrease in yield of the device.